a. Field of the Invention
The present invention relates to communication systems. In particular, the present invention relates to the synchronization of time signals amongst a plurality of communications system components such as cable modems.
b. Description of Related Art
As information becomes increasingly more available on communication networks such as a LAN or over the Internet, the development of new methods and apparatus for sending and receiving this information more quickly between communication system users has become an important issue. For instance, one-way and two-way cable modems, both internal and external, based on the Multimedia Cable Network System (MCNS) Data-Over-Cable Interface Specifications (DOCSIS) standard, are currently available to consumers to access data over the Internet at speeds far in excess of those previously attainable by standard analog telephone modems. An external cable modem is a complete, self contained unit which is housed in its own enclosure, separate from a personal computer (PC), as opposed to an internal cable modem which is designed as a peripheral card on a printed circuit board (PCB) inserted into a PC. Two-way cable modems receive modulated data from a head-end (H/E) controller over a 75-ohm coaxial cable (the same cable found in residential housing) and send back upstream data over this same cable to the headend controller. A one-way cable modem receives data from the headend on a 75-ohm cable, but transmits upstream data back to the headend using a standard analog telephone modem (i.e. 28/33/56 kbps). In each case the headend controller exists to serve a number of subscribers to the cable modem service.
Downstream (D/S) data for all subscribers is interleaved in time and continuously transmitted down the cable. The downstream data in one instance occupies a 6 MHz wide channel with a center frequency between 54-850 MHz. Raw D/S data rates may range between 30-40 Mbps. However, most subscribers will see much less than this since the downstream bandwidth needs to be shared with many other subscribers as stated earlier. A typical cable plant installation will have between 500 and 2000 subscribers on a particular downstream channel. In addition, there is some degree of overhead required for header data and forward error correction. This serves to lower the true raw data rate somewhat. If every subscriber were receiving data continuously, then the effective raw data rate seen by any one subscriber would be 1/500 or 1/2000 of the maximum D/S data rate possible after subtracting overhead. However, computer-computer data communications tend to be bursty in nature, and not every subscriber is logged on at the same time. This means that under nominal loading, each subscriber can expect to see effective D/S data rates in the range of 100""s of kbps. FIG. 1 illustrates the typical D/S data stream 100 for a cable modem system. Notice that the D/S data contains both data for each modem 102 and general management packets 104.
In the case of D/S data, each cable modem continuously monitors the D/S channel. When data addressed to a particular modem is received, the modem takes appropriate action. All other data which is not addressed to that modem is ignored. In the case of the two-way cable modem system, all replies are transmitted on the upstream (U/S) channel of the coaxial cable back to the headend controller. In one instance of the typical two-way cable modem system, there is no contention (or collisions) on the D/S channel, because no modem ever uses the D/S data channel frequency for U/S data. For, in this system U/S data occupies channels of 200 kHz-3.2 Mz wide in the range of 5-42 MHz. The headend controller is the single system component which completely decides what data to what modem is sent when on the D/S channel.
However, in the case of the U/S data channel for a two-way system with a number of subscribers there are many cable modems which must compete with each other in some fashion to send their data back to the headend controller. Of course, if two modems try and send data at the same time to the headend controller, a collision can occur. Unlike a typical network such as an Ethernet, the individual cable modems can not xe2x80x9chearxe2x80x9d (i.e. receive or monitor) data from other cable modems. This is due mostly to the one-way transmission property of the cable plant (due to directive circuit elements, such as power splitters, amplifiers and directional couplers) and also due to the large time delays inherent in the cable plant due to the large distances involved in the cable routing. FIG. 2 shows a diagram of a typical cable plant. The typical cable plant includes a headend controller 200 which is coupled to the rest of the plant via, in one instance, fiber optic cable 210. Data is passed from the headend 200 to the cable modems such as modems 1, 2, 3, 4, N, and N+1, via a network of combiners such as 2-way combiners 215, and 4-way combiners 220. Similarly, in a two-way system, data is passed from the cable modems to the headend 200 over the same network.
Therefore, it is up to the headend controller to decide which subscriber modem sends U/S data at what time. In one instance this is done by using a system of mini-slot time increments of around 6.25 usec each. Each modem is assigned a time in which it can transmit its signal so as to arrive at the headend controller in time-interleaved fashion, thereby not colliding with U/S data from other modem subscribers. For all of this to work, the headend controller performs a ranging operation to determine the time delay from each modem. The headend controller then figures out for each modem a time slot in which it can send its data so as to not collide with the U/S data from other modems at the headend controller. This sequence of events is illustrated by FIGS. 3(a)-(b) in which FIG. 3(a) shows a timing diagram illustrating how the U/S data from a number of cable modems looks by the time it reaches the headend controller associated with those cable modems. The blocks labeled Modem #1, Modem #234, Modem #57, Modem #465, Modem #1, and Modem #33 represent data sent from those respective modems to the headend 200. The blocks of time labeled guard time represent time slots in which data is not expected to be sent from any of the modems to the headend 200xe2x80x94this helps to minimize collisions of upstream data by minimizing the chance of data timeslot overlap. FIG. 3(b) depicts a timing diagram that illustrates a hypothetical example of the actual time that each U/S packet was sent, so as to arrive at the headend controller at the proper time. The details of this process are complicated and are described more fully in the MCNS DOCSIS specifications referred to earlier and which are hereby incorporated by reference.
As can be seen from the above discussion, in order for the U/S data synchronization to work, each modem needs an accurate local clock reference which is precisely in synchronization with the headend clock. In general, accurate clock references are derived from an accurate crystal oscillator whose frequency is divided down to the desired time interval. Since there is typically only one headend controller per every 500-2000 subscribers, it makes economic sense to buy a highly precise and accurate crystal oscillator. For this reason, headend crystal oscillators are typically of the expensive temperature-compensated type with frequency (and hence time) variations of just a few parts-per-million (ppm). However, in the case of an individual cable modem intended for the consumer market, cost is of paramount importance. Therefore, a typical cable modem contains an inexpensive, non-temperature-compensated crystal oscillator with an accuracy of 50-100 ppm as illustrated in FIG. 4(a) which shows a typical standard crystal oscillator configured to output a digital clock output to be used by the rest of the cable modem""s integrated circuitry. Some of this variation comes from the wider temperature range each subscriber modem is expected to operate over, and some variation due to initial set-on accuracy.
Currently known methods of synchronizing modem clocks with headend clocks try and tune the local modem crystal oscillator to match the frequency of the headend clock. This is most often done by using a voltage-controlled crystal oscillator (VCXO) to slightly vary the local modem oscillator. A circuit designed to implement the VCXO approach of synchronization is illustrated in FIG. 4(b). The element used in such a circuit is a voltage-variable capacitorxe2x80x94often implemented with a varactor diode such as diode D1 of FIG. 4(b). This circuit operates to vary the capacitance of capacitor C1 and therefore the oscillating frequency of the Crystal Oscillator. In this type of circuit, successive timestamps from the headend are compared to time intervals from the local modem by the CPU 450. If the local modem is running too fast, the frequency of the modem clock oscillator is reduced. Likewise, if the local clock is running too slow, the modem clock oscillator is increased. This can be done in one instance by providing digital signals from the CPU 450 to the Digital/Analog Converter 455 which in turn varies the voltage at the input of resistor Rx in order to adjust the capacitance of C1 and in turn adjust the Crystal Oscillators frequency.
There are a number of disadvantages with this approach. First, many successive timestamps need to be gotten from the headend. In order to avoid the problem of over-correction, and hence loop stability problems, corrections to the VCXO need to be kept small, so as to not overshoot the desired final frequency. Taking many timestamps can consume many seconds or even minutes (recall that each timestamp comes at 200-600 msec intervals). The problem is further exacerbated by the slow response of the crystal. Most crystals are very high-Q devices which take a long time to change to a new frequency. In addition, all of the components driving the VCXO are analog, thereby subject to temperature and aging problems as well as non-linearities.
Therefore, what is needed is a new method and apparatus which is capable of accurately synchronizing the clock of each cable modem of a two-way cable modem system with the clock of its headend controller in a cost-effective manner which avoids the aforementioned problems of currently known synchronization methods.
As discussed above, currently known methods of synchronizing local clocks of communications system components with the master clock of the communications system control component try and tune the local modem crystal oscillator to match the frequency of the master clock. This is most often done by using a voltage-controlled crystal oscillator (VCXO) to slightly vary the local oscillator. There are a number of disadvantages with this approach. In order to avoid the problem of over-correction, and hence loop stability problems, corrections to the VCXO need to be kept small, so as to not overshoot the desired final frequency. Thus, many successive timestamps need to be gotten from the control component thereby consuming many seconds or even minutes. The problem is further exacerbated by the slow response of the crystal. In addition, all of the components driving the VCXO are analog and thereby subject to temperature and aging problems as well as non-linearities.
Accordingly, the present invention provides a method and apparatus for synchronizing the local clock of a transceiver in a communications system with the master clock of its corresponding communications system control unit such that some of the problems associated with currently known synchronization methods are avoided.
In one embodiment of the present invention a method of synchronizing the local clock of a transceiver with the master clock of a control unit to which the transceiver is coupled is provided. The method of this embodiment comprises receiving a first timestamp with the transceiver, wherein the first timestamp comprises a signal generated by the control unit in response to the value of the master clock at the time the first timestamp signal is generated. Further, the method includes generating a first transceiver time reference with the transceiver device in response to the receipt of the first timestamp and generating a correction factor in response to the difference of the first timestamp and the first transceiver time reference. Finally, the method includes generating a synchronized downstream reference signal by adjusting an output clock signal of the local clock in response to the correction factor. In one embodiment of this method, the communications system is a cable modem system in which the transceiver is a cable modem, and the control unit is a headend unit. Further, the steps of generating a correction factor and generating a synchronized downstream reference signal are performed by digital logic in one embodiment.
In a further embodiment of the invention, the method further comprises receiving a second timestamp with the transceiver, wherein the second timestamp comprises a signal generated by the control unit in response to the value of the master clock at the time the second timestamp signal is generated and generating a second transceiver time reference with the transceiver device in response to the receipt of the second timestamp. A control unit difference time is then generated comprising the difference of the first and second timestamps. A transceiver difference time comprising the difference of the first and second transceiver time references is also generated in addition to a clock error time wherein the clock error time comprises the difference of the control unit difference time and the transceiver difference time. The correction factor in this embodiment is generated in response to the clock error time.
In another instance of the method, the first and second transceiver time references comprise time signals generated by the transceiver device in response to the values of the local clock at the times the first and second timestamps respectively are received.
In still another embodiment, the correction factor comprises an offset signal that corresponds to the clock error time divided by the transceiver difference time. In this embodiment, the offset signal is representative of the local clock error per local clock pulse. In generating the synchronized downstream reference signal, this embodiment of the method provides for adding the offset signal into an accumulator device on each pulse of the local clock and adjusting the output clock signal when the accumulator device rolls over.
The above embodiment can be further characterized in that the correction factor may also comprise an addsub signal that indicates if the local clock is either running faster or slower than the master clock. Given the value of the addsub signal, the local clock output can be adjusted either upward or downward accordingly.
In still another embodiment of the invention the method may comprise the further step of generating a synchronized upstream reference signal. In this instance, the synchronized upstream reference signal comprises a time signal utilized by the transceiver to determine when the transceiver can transmit a first output signal to the control unit such that the first output signal does not collide with a second output signal transmitted by one or more other transceivers in the system that are connected to the control unit. In one particular instance of this embodiment the step of generating the upstream reference signal comprises either adding or subtracting a delay offset time from the downstream reference signal. The delay offset time in this case comprises the amount of time required for a ranging time signal to be received by the transceiver after the ranging time signal is transmitted by the control unit.
In an alternate characterization of the present invention, the invention is described as a cable modem apparatus in a communications system comprising a headend unit including a master clock and a plurality of cable modems coupled to the headend unit. In this characterization, the cable modem apparatus comprises an input/output node coupled to the headend unit and a receiver that is coupled to the input/output node and that receives a first timestamp generated by the headend unit in response to the value of the master clock at the time the first timestamp signal is generated. The cable modem also includes a local clock configured to operate at substantially the same frequency as the master clock and a synchronization counter that is coupled to the receiver. The synchronization counter generates a first cable modem time reference in response to the receipt of the first timestamp, and it also includes a correction signal generator that generates a correction factor in response to the difference of the first timestamp and the first cable modem time reference and a correction circuit that generates a synchronized downstream reference signal by adjusting an output clock signal of the local clock in response to the correction factor. In this embodiment, the correction signal generator and the correction circuit may comprise digital logic.
In another embodiment, the correction circuit also generates a synchronized upstream reference signal. The synchronized upstream reference signal comprises a time signal utilized by the cable modem to determine when the cable modem can transmit a first output signal to the headend unit such that the first output signal does not collide with a second output signal transmitted by a different cable modem in the system. In one instance of this embodiment, the correction circuit generates the upstream reference signal by either adding or subtracting a delay offset time from the downstream reference signal. In one case, the delay offset time comprises the amount of time required for a ranging time signal to be received by the cable modem after the ranging time signal is transmitted by the headend.
In another embodiment, the invention can be further characterized in that the receiver receives a second timestamp that is generated by the headend unit in response to the value of the master clock at the time the second timestamp signal is generated. Also, the synchronization counter generates a second cable modem time reference in response to the receipt of the second timestamp. Lastly, the correction signal generator generates the correction factor in response to the difference of a headend difference time and a cable modem difference time. In this instance, the headend difference time comprises the difference of the first and second timestamps, and the cable modem difference time comprises the difference of the first and second cable modem time references.
In one instance of the above embodiment, the first and second cable modem time references comprise a time signals generated by the cable modem in response to the values of the local clock at the times the first and second timestamps are respectively received.
In still another embodiment, the correction factor comprises an offset signal that corresponds to the clock error time divided by the transceiver difference time. In this embodiment, the offset signal is representative of the local clock error per local clock pulse. In generating the synchronized downstream reference signal, this embodiment provides for adding the offset signal into an accumulator device on each pulse of the local clock and adjusting the output clock signal when the accumulator device rolls over.
The above embodiment can be further characterized in that the correction factor may also comprise an addsub signal that indicates if the local clock is either running faster or slower than the master clock. Given the value of the addsub signal, the local clock output can be adjusted either upward or downward accordingly.
Lastly, the present invention may also be characterized as an apparatus for synchronizing the local clock of a transceiver that is coupled to a control unit with the master clock of the control unit. In this characterization, the apparatus comprises a means for receiving a first timestamp, wherein the first timestamp comprises a signal generated by the control unit in response to the value of the master clock at the time the first timestamp signal is generated. Also included is a means for generating a first transceiver time reference in response to the receipt of the first timestamp, a means for generating a correction factor in response to the difference of the first timestamp and the first transceiver time reference, and a means for generating a synchronized downstream reference signal that comprises an output clock signal of the local clock adjusted in response to the correction factor. In one instance, the transceiver device comprises a cable modem and the control unit comprises a headend unit. In a further instance of this embodiment, the means for generating a correction factor and the means for generating a synchronized downstream reference signal comprise digital logic.
A further embodiment of this apparatus includes a means for generating a synchronized upstream reference signal. In one case, the synchronized upstream reference signal comprises a time signal utilized by the transceiver to determine when the transceiver can transmit a first output signal to the control unit such that the first output signal does not collide with a second output signal transmitted by another transceiver in the system. In one instance of this embodiment, the generation of the upstream reference signal comprises either adding or subtracting a delay offset time from the downstream reference time. The delay offset time in one case comprises the amount of time required for a ranging time signal to be received by the transceiver after the ranging time signal is transmitted by the control unit.
In still another embodiment, the correction factor is generated in response to the value of a clock error time, and the apparatus also includes a means for receiving a second timestamp, wherein the second timestamp comprises a signal generated by the control unit in response to the value of the master clock at the time the second timestamp is generated. Also included in this embodiment are a means for generating a second transceiver time reference in response to the receipt of the second timestamp, a means for generating a control unit difference time comprising the difference of the first and second timestamps, a means for generating a transceiver difference time comprising the difference of the first and second transceiver time references, and a means for generating the clock error time wherein the clock error time comprises the difference of the control unit difference time and the transceiver difference time.
In still another embodiment, the correction factor comprises an offset signal that corresponds to the clock error time divided by the transceiver difference time. In this embodiment, the offset signal is representative of the local clock error per local clock pulse. In generating the synchronized downstream reference signal, this embodiment of the apparatus includes a means for adding the offset signal into an accumulator device on each pulse of the local clock and a means for adjusting the output clock signal when the accumulator device rolls over. The above embodiment can be further characterized in that the correction factor may also comprise an addsub signal that indicates if the local clock is either running faster or slower than the master clock. Given the value of the addsub signal, the local clock output can be adjusted either upward or downward accordingly.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description, and the claims which follow.